1. Field of the Invention
The present invention relates to a method of fabricating a power semiconductor device, and more particularly, to a method of fabricating a power semiconductor device that has a high breakdown voltage using a semi-insulating polycrystalline silicon (SIPOS) film.
2. Description of the Related Art
A recent trend towards large, high-capacity applications has created a need for a power semiconductor device having a high breakdown voltage, high-speed switching, and high current capability. The power semiconductor device particularly requires a low saturation voltage to lower power loss in a conductive state when allowing a significantly large current to flow. High breakdown voltage, a fundamental requirement for power semiconductor device, means that the power semiconductor devices can resist a high reverse voltage, as may be applied when the device is switched off or at the moment of switching off.
Meanwhile, the breakdown voltage of a semiconductor device is determined by a depletion region, which is formed at a P-N junction portion, since most of the voltage applied to the P-N junction portion is applied to the depletion region. The breakdown voltage has been known to be affected by the curvature of the depletion region. In other words, at a planar junction an electric field is concentrated at a curved portion rather than a flat portion. Accordingly, an avalanche breakdown is easily generated at the edge of the junction, and the breakdown voltage of the entire depletion region is reduced.
Various techniques have been proposed to prevent the electric field from concentrating at the edge of a junction. Among them, there are included: (1) a method of forming a field plate on a substrate of a field region adjacent to the edge of the planar junction (reference document: "Power semiconductor device", 1996, B. J. Baliga, pages 100-102); (2) a method of forming a field limiting ring as an impurity layer having a conductive type opposite to the junction in the field region of the substrate; (3) and a method of forming a semi-insulating polycrystalline silicon (SIPOS) layer on a substrate on which the planar junction is formed. These methods all increase the breakdown voltage by enhancing the curvature of a depletion region.
The method using the SIPOS film is a relatively simple process, and can stabilize the characteristics of a device by removing a surface-state effect from a silicon substrate, while simultaneously increasing a breakdown voltage. As a result, this method has attracted attention recently.
FIGS. 1 and 2 are sectional views of a conventional power transistor using a SIPOS film.
Referring to FIG. 1, first conductive high concentration (N.sup.+) and low concentration (N.sup.-) collector regions 2 and 4 are sequentially formed to make a bottom layer. A second conductive P.sup.+ base region 6 is formed in the bottom layer, and a first conductive N.sup.+ emitter region 8 is formed in the base region 6. An N.sup.+ channel stop region 10 for device isolation is formed in a field region separated by a predetermined interval from the base region 6.
Also, an insulating film 12 (preferably an oxide film) and a semi-insulating polycrystalline silicon (SIPOS) film 14 are sequentially formed over the semiconductor substrate. A base electrode 16, an emitter electrode 18, and an equipotential metal ring 22 are formed to contact the base region 6, the emitter region 8, and the channel stop layer 10, respectively, through contact holes. A collector electrode 20 is formed on the other surface of the high-concentration (N.sup.+) collector region 2.
According to the conventional power transistor described above, the insulating film 12 and the SIPOS film 14 are deposited and then etched, and then the base electrode 16, the emitter electrode 18, and the equipotential metal ring 22 are formed. At this time, a dry or wet etching method is employed.
However, the process of dry-etching the oxide film 12 is expensive, thus degrading productivity. When wet etching is employed, voids (V) are generated under the SIPOS film 14 as shown in FIG. 2, because of the isotropic etching characteristics of the wet etching method. The voids formed between the oxide film 12 and the electrodes 18 and 22 have a bad influence on the device's reliability, due to humidity and expansion coefficient difference. In particular, processes for forming a base contact and for forming an emitter contact are usually conducted simultaneously when fabricating a transistor, so that a void at the emitter contact is enlarged due to the over-etching of the emitter contact.